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به سوی مهندسی سیستم های بینایی کامپیوتری: از وب تا FPGA
Towards Engineering Computer Vision Systems: From the Web to FPGAs
Computer vision is an interdisciplinary field to obtain high-level understanding from digital images. It has many applications that impact our daily lives, such as automation, entertainment, healthcare, etc. However, computer vision is very challenging. This is in part due to the intrinsically difficult nature of the problem and partly due to the complexity and size of visual data that need to be processed. To be able to deploy computer vision in many practical use cases, sophisticated algorithms and efficient implementations are required.
In this thesis, we consider two platforms that are suitable for computer vision processing, yet they were not easily accessible to algorithm designers and developers: the Web and FPGA-based accelerators. Through the development of open-source software components, we highlight challenges associated with vision development on each platform and demonstrate opportunities to mitigate them.
Field Programmable Gate Arrays (FPGA)s are a promising solution to mitigate the computational cost of vision algorithms through hardware pipelining and parallelism. However, an efficient FPGA implementation of computer vision algorithms requires hardware design expertise and a considerable amount of engineering person-hours. We show that graph-based specifications, such as OpenVX can significantly improve FPGA design productivity. Since such abstraction lacks implementation details, a vision algorithm designer can only focus on the algorithm itself and rely on another party with hardware knowledge to implement the design efficiently on a specific platform. During this process, different implementation configurations that satisfy various design constraints, such as performance and power consumption, can be explored. Furthermore, the graph-based model permits system-level optimizations that are not possible with traditional function-level acceleration. Towards this goal, we develop a framework that optimizes and implements vision algorithms that are described in OpenVX spec on different FPGA architectures. This framework hides low-level hardware optimization and implementation details from computer vision algorithm designers and enables them to quickly develop and verify FPGA implementations of vision algorithms without sacrificing performance.
بررسی طراحی درون زبانی در سیستم عامل ها
Exploring Intralingual Design in Operating Systems
Safe languages have been used to avoid memory safety violations in Operating Systems (OS). Software isolation techniques have been presented as a way to eschew the high cost of hardware isolation. Single Address Space/ Single Privilege Level (SAS/SPL) OSes use type and memory-safe languages to avoid system calls and changing address spaces. This thesis extends the use of safe languages in OSes to provide benefits beyond memory safety and avoiding the overhead of hardware isolation. We demonstrate that intralingual OS design, using language-level mechanisms to ensure OS correctness, allows us to build systems that can provide isolation without specialized hardware. Intralingual system design also allows us to transfer responsibilities that were previously the OS developer's to the compiler, such as memory and power management. We use Rust, a safe systems programming language with a runtime similar to C, to apply intralingual design to 4 areas: the heap, Inter-Task Communication (ITC), networking, and power management. We present a SAS heap shared by multiple processes that can decrease fragmentation by up to 30% over per-task heaps. We implement a shared-memory ITC channel that is 20% faster than the fastpath IPC of a leading microkernel. We use type safety and Rust’s ownership feature to safely share a Network Interface Card’s (NIC) resources among applications while ensuring direct access to hardware. Lastly, we demonstrate that a whole class of power management bugs can be eliminated when shifting reference counting to the compiler.